System LSI circuits, that are used in a wide variety of processing such as image processing, encryption processing, filter processing and decoding processing and the like, involve various types of input/output signals, various processing algorithms or a variety of required time-related capabilities. A system LSI circuit incorporates a processor that has a single instruction set composed of performance-oriented instructions suited to the processing required. In this case, if the content of processing executed by the system LSI circuit includes, e.g., both processing suited to an instruction set oriented toward controll performance and an instruction set oriented toward signal processing performance, overall processing cannot be executed at high speed with just a single processor.
A processor adapted for being switched between a reduced instruction set and a high-performance instruction set in response to a speed changeover instruction is described in the specification of Japanese Patent Kokai Publication JP-A-8-106383 (termed as Patent Reference 1) as means capable of selecting among an optimum program, processing and processing speed in accordance with the nature of processing to be executed. FIG. 12 illustrates the structure of the processor described in the Patent Reference 1. Here a high-speed program written in RISC instructions (a reduced instruction set) and a low-speed program written in CISC instructions (a complex instruction set) have been stored in a main memory 201 in shared fashion as an application program having a speed changeover instruction as a boundary between them. An R/C register 209 stores a low-speed mode or a high-speed mode in an R/C flag.
When the R/C flag stored in the R/C register 209 is indicative of the high-speed mode, a decoder selection circuit 206 supplies a RISC decoder 207 with the high-speed program (RISC instructions) that have been fetched from the main memory 201 and stored in an instruction register 205. If the speed changeover instruction (low-speed changeover instruction), which is a RISC instruction, is now executed upon being decoded by the RISC decoder 207, the low-speed mode is set in the R/C flag. When this is done, a clock selection circuit 218 changes over the selected state to change an execution clock φ′ from a master clock φ to a frequency-divided clock obtained by frequency-dividing the master clock φ by n in an n frequency divider 219. Further, the decoder selection circuit 206 changes over the selection state and supplies a CISC decoder 211 with the low-speed program (CISC instruction), which has been fetched from the main memory 201 and stored in the instruction register 205, via a mapping unit 208 and address selector 210.
If the speed changeover instruction (high-speed changeover instruction), which is a CISC instruction, is executed upon being decoded by a CISC decoder 211, the high-speed mode is set in the R/C flag. When this is done, the clock selection circuit 218 changes over the selected state to change the execution clock φ′ to the master clock φ from the frequency divided clock obtained on frequency division by n by the n frequency divider 219. Further, the decoder selection circuit 206 changes over the selected state and supplies the RISC decoder 207 with the RISC instruction that has been fetched from the main memory 201 and stored in the instruction register 205. Thus, the processor 200 switches between the high-speed instruction set and the low-speed instruction set dynamically in response to the speed changeover instruction inserted at the boundary between the low- and high-speed programs.
Art having a plurality of instruction sets from among which any instruction set is selected for use by employing a predetermined bit, which usually is not used, of a program counter (PC) register is described in the specification of Japanese Patent Kokai Publication No. JP-P2002-328804A (Patent Reference 2) as other means whereby an instruction set to be used is changed over dynamically in response to a changeover instruction included in an application program. This technique differs from that of Patent Reference 1 in that it does not require the dedicated R/C register 209 (see FIG. 12) for changing over the instruction set.
[Patent Reference 1]
Japanese Patent Kokai Publication JP-A-8-106383
[Patent Reference 2]
Japanese Patent Kokai Publication JP-P2002-328804A